Fast DSP Implementation of a Low Complexity LDPC Decoder

被引：0
|
作者：
Razi, Mouhcine [1 ]
Benhayoun, Mhammed [1 ]
Mansouri, Anas [1 ]
Madi, Abdessalam Ait [1 ]
Ahaitouf, Ali [1 ]
机构：
[1] USMBA Univ, ERSI Lab, Fes, Morocco
来源：
2019 INTERNATIONAL CONFERENCE ON WIRELESS TECHNOLOGIES, EMBEDDED AND INTELLIGENT SYSTEMS (WITS) | 2019年
关键词：
LDPC decoders; Min Sum Algorithm; Horizontal Shuffled Scheduling; DSP implementation;
D O I：
10.1109/wits.2019.8723838
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Belief Propagation (BP) algorithm is known as the most efficient algorithm in terms of convergence speed. But this algorithm has a very high level of computational complexity. The MM Sum Algorithm (MSA) permits to reduce this computational complexity but with some performances degradations. In this paper we recommend a new approach with more simplified algorithm, that allows to get performances near to these of the BP algorithm by adopting a new version of the MSA algorithm. This last uses Horizontal Shuffled (HS) scheduling instead of the usually used flooding scheduling. This algorithm was successfully implemented on the Digital Signal Processor (DSP). The results obtained after implementation show that the proposed version of the MSA algorithm does not only improve the decoding performance but also decreases the number of iterations necessary for the decoding of the LDPC codes.
引用
收藏
页数：5
相关论文
共 50 条
  • [21] Low Complexity LDPC Decoder with Modified Sum-Product Algorithm
    Chen Qian
    Weilong Lei
    Zhaocheng Wang
    Tsinghua Science and Technology, 2013, 18 (01) : 57 - 61
  • [22] Architecture of a low-complexity non-binary LDPC decoder
    Voicila, Adrian
    Declercq, David
    Verdier, Francois
    Fossorier, Marc
    Urard, Pascal
    2008 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 2008, : 197 - +
  • [23] Low Complexity Generalized-LDPC Decoder Based on Trellis Splicing
    Zhou, Xuan
    Ma, Zheng
    Li, Li
    Xiao, Ming
    IEEE COMMUNICATIONS LETTERS, 2021, 25 (03) : 830 - 834
  • [24] Low Complexity LDPC Decoder with Modified Sum-Product Algorithm
    Qian, Chen
    Lei, Weilong
    Wang, Zhaocheng
    TSINGHUA SCIENCE AND TECHNOLOGY, 2013, 18 (01) : 57 - 61
  • [25] Low Complexity Implementation of Slim - HEVC Decoder Design
    So, Jaehyuk
    Oh, Kyungmook
    Kim, Jaeseok
    PROCEEDINGS OF 2016 IEEE ADVANCED INFORMATION MANAGEMENT, COMMUNICATES, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (IMCEC 2016), 2016, : 483 - 486
  • [26] VLSI Implementation of Low -Complexity Reed Solomon Decoder
    Mhaske, Samir D.
    Ghodeswar, Ujwala
    Sarate, G. G.
    2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,
  • [27] Fast Convergence and Low Complexity Stochastic Turbo Decoder
    Zhang, Zhenbing
    Hu, Jianhao
    Chen, Jienan
    Han, Kaining
    2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 659 - 662
  • [28] LDPC Decoder Implementation Using FPGA
    Kiaee, Mahdie
    Gharaee, Hossein
    Mohammadzadeh, Naser
    2016 8TH INTERNATIONAL SYMPOSIUM ON TELECOMMUNICATIONS (IST), 2016, : 167 - 173
  • [29] Efficient implementation technique of LDPC decoder
    Leung, WK
    Lee, WL
    Wu, A
    Ping, L
    ELECTRONICS LETTERS, 2001, 37 (20) : 1231 - 1232
  • [30] An FPGA implementation of array LDPC decoder
    Sha, Jin
    Gao, Minglun
    Zhang, Zhongjin
    Li, Li
    Wang, Zhongfeng
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1675 - +
12345