Design Study of the Bump on Flexible Lead by FEA for Wafer Level Packaging

被引：0

作者：

Eidner, I. ^{[1
]}

Wunderle, B. ^{[2
]}

Pan, K. L. ^{[3
]}

Wolf, M. J. ^{[2
]}

Ehrmann, O. ^{[1
]}

Reichl, H. ^{[1
]}

机构：

[1] Tech Univ Berlin, Gustav Meyer Allee 17A,TIB 4-2-1, D-13355 Berlin, Germany

[2] Fraunhofer Inst Reliabil & Microintegrat, D-13355 Berlin, Germany

[3] Guilin Univ Elect Technol, Guilin 541004, Peoples R China

来源：

EUROSIME 2009: THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS | 2009年

关键词：

RELIABILITY;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Bump on Flexible Lead (BoFL) is a chip-to-substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer (RDL) embedded in a polyimide-bridge which is located over an air gap. Since the stress due to CTE mismatch is then accommodated within the flexible lead, the risk of solder fatigue decreases. The new failure risks are mainly related to fatigue of the copper RDL. Therefore a design study of the flexible lead by finite element analysis (FEA) was performed. The parameters investigated were the polyimide thickness, the thickness of the copper RDL and the shape of the copper RDL. The results obtained from the simulation study are useful to form design guidelines for enhanced board level reliability of the BoFL-WLP.

引用

页码：348 / +

页数：3

共 50 条

[21] Wafer-level packaging
Van Driel, Willem Dirk
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2007, 30 (03): : 358 - 358
[22] Wafer level packaging of MEMS
Esashi, Masayoshi
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2008, 18 (07)
[23] HMIC Wafer Level Packaging
Boles, Timothy
Hoag, David
Barter, Margaret
Giacchino, Richard
Hogan, Paul
Goodrich, Joel
2009 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC 2009), 2009, : 423 - 426
[24] Wafer level packaging for CSPs
Hou, Michelle
Semiconductor International, 1998, 21 (08): : 305 - 306
[25] HMIC Wafer Level Packaging
Boles, Timothy
Hoag, David
Barter, Margaret
Giacchino, Richard
Hogan, Paul
Goodrich, Joel
2009 EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, 2009, : 1776 - 1779
[26] Flip chip wafer level packaging of a flexible chip scale package (CSP)
Hotchkiss, G
Amador, G
Edwards, D
Hundt, P
Stark, L
Stierman, R
Heinen, G
1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 555 - 562
[27] Copper pillar bump design optimization for lead free flip-chip packaging
K. M. Chen
T. S. Lin
Journal of Materials Science: Materials in Electronics, 2010, 21 : 278 - 284
[28] Copper pillar bump design optimization for lead free flip-chip packaging
Chen, K. M.
Lin, T. S.
JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2010, 21 (03) : 278 - 284
[29] Reliability Simulation with the Finite Element Analysis (FEA) of Redistribution Layer in Fan-out Wafer Level Packaging
Okada, Yuji
Fujii, Atsushi
Ono, Kenta
Kariya, Yoshiharu
JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY, 2020, 33 (02) : 171 - 176
[30] Printed Circuit Board Electrical Design for Wafer-Level Packaging
Wu, Boping
Mo, Tingting
2011 12TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY AND HIGH DENSITY PACKAGING (ICEPT-HDP), 2011, : 302 - 305

← 1 2 3 4 5 →