Design Study of the Bump on Flexible Lead by FEA for Wafer Level Packaging

被引：0
|
作者：
Eidner, I. [1 ]
Wunderle, B. [2 ]
Pan, K. L. [3 ]
Wolf, M. J. [2 ]
Ehrmann, O. [1 ]
Reichl, H. [1 ]
机构：
[1] Tech Univ Berlin, Gustav Meyer Allee 17A,TIB 4-2-1, D-13355 Berlin, Germany
[2] Fraunhofer Inst Reliabil & Microintegrat, D-13355 Berlin, Germany
[3] Guilin Univ Elect Technol, Guilin 541004, Peoples R China
来源：
EUROSIME 2009: THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS | 2009年
关键词：
RELIABILITY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The Bump on Flexible Lead (BoFL) is a chip-to-substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer (RDL) embedded in a polyimide-bridge which is located over an air gap. Since the stress due to CTE mismatch is then accommodated within the flexible lead, the risk of solder fatigue decreases. The new failure risks are mainly related to fatigue of the copper RDL. Therefore a design study of the flexible lead by finite element analysis (FEA) was performed. The parameters investigated were the polyimide thickness, the thickness of the copper RDL and the shape of the copper RDL. The results obtained from the simulation study are useful to form design guidelines for enhanced board level reliability of the BoFL-WLP.
引用
收藏
页码：348 / +
页数：3
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