Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

被引：6
|
作者：
Zhang, SD [1 ]
Han, RQ
Sin, JKO
Chan, M
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
[2] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Hong Kong, Peoples R China
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 08期
关键词：
double-gate; lightly doped drain (LDD); self-aligned; thin-film transistor (TFT);
D O I：
10.1109/TED.2002.801232
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10(-9) A/mum to 10(-12) A/mum. The orVoff current ratio is increased by three orders of magnitude accordingly from around 104 to 10(7).
引用
收藏
页码：1490 / 1492
页数：3
相关论文
共 50 条
  • [21] An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve Multifold Transient Frequency Enhancement
    Daulatabad, Shreeniwas
    Swain, Peeyusha Saurabha
    Gossner, Harald
    Baghini, Maryam Shojaei
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (09) : 5074 - 5081
  • [22] A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application
    Zhang, SD
    Lin, XN
    Huang, R
    Han, RQ
    Chan, MS
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (11) : 2297 - 2300
  • [23] Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method
    Saad, Ismail
    Ismail, Razali
    MICROELECTRONICS JOURNAL, 2008, 39 (12) : 1538 - 1541
  • [24] Two gates are better than one - A planar self-aligned double-gate MOSFET technology to achieve the best on/off switching ratios as gate lengths shrink
    Solomon, PM
    Guarini, KW
    Zhang, Y
    Chan, KK
    Jones, EC
    Cohen, GM
    Krasnoperova, A
    Ronay, M
    Dokumaci, O
    Hovel, HJ
    Bucchignano, JJ
    Cabral, C
    Lavoie, C
    Ku, V
    Boyd, DC
    Petrarca, KS
    Yoon, JH
    Babich, IV
    Treichler, J
    Kozlowski, PM
    Newbury, JS
    D'Emic, CP
    Sicina, RM
    Benedict, J
    Wong, HSP
    IEEE CIRCUITS & DEVICES, 2003, 19 (01): : 48 - 62
  • [25] Self-aligned planar double-gate field-effect transistors fabricated by a source/drain first process
    Sakamoto, K
    Huda, MQ
    Ishii, K
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2005, 44 (1-7): : L147 - L149
  • [26] Single-electron charge sensor self-aligned to a quantum dot array by double-gate patterning process
    Kuno, Takuma
    Utsugi, Takeru
    Tsuchiya, Ryuta
    Lee, Noriyuki
    Mine, Toshiyuki
    Yanagi, Itaru
    Mizokuchi, Raisei
    Yoneda, Jun
    Kodera, Tetsuo
    Saito, Shinichi
    Hisamoto, Digh
    Mizuno, Hiroyuki
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2025, 64 (01)
  • [27] Impact of Hydrogenation Process on Performance of Self-Aligned Metal Double-Gate LT Poly-Si TFTs
    Shika, Yusuke
    Bessho, Takuro
    Okabe, Yasunori
    Ogata, Hiroyuki
    Kamo, Shinya
    Kitahara, Kuninori
    Hara, Akito
    2012 19TH INTERNATIONAL WORKSHOP ON ACTIVE-MATRIX FLATPANEL DISPLAYS AND DEVICES (AM-FPD): TFT TECHNOLOGIES AND FPD MATERIALS, 2012, : 123 - 126
  • [28] SELF-ALIGNED DOUBLE-GATE (DG) VERTICAL MOSFET's USING OBLIQUE ROTATING IMPLANTATION (ORI) METHOD WITH REDUCED PARASITIC CAPACITANCE
    Saad, Ismail
    Riyadi, Munawar A.
    Ismail, Razali
    Arora, Vijay K.
    ICSE: 2008 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2008, : 604 - +
  • [29] Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate
    Ogata, Hiroyuki
    Ichijo, Kenji
    Kondo, Kenji
    Hara, Akito
    IEICE TRANSACTIONS ON ELECTRONICS, 2013, E96C (02): : 285 - 288
  • [30] Self-Aligned Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate
    Sasaki, Shun
    Ogata, Hiroyuki
    Hara, Akito
    PROCEEDINGS OF 2013 TWENTIETH INTERNATIONAL WORKSHOP ON ACTIVE-MATRIX FLATPANEL DISPLAYS AND DEVICES (AM-FPD 13): TFT TECHNOLOGIES AND FPD MATERIALS, 2013, : 251 - 254
12345