Signal Integrity Analysis of DDR3 High-Speed Memory Module

In this paper, a complete simulation methodology is introduced to analyze the signal integrity in a Double Data Rate (DDR3) high-speed memory module. The equivalent models of the first-level package and various discontinuities in Printed Circuit Board (PCB) are extracted, and then linked together by using general transmission-line models for the interconnections. Good agreements between the simulated and measured scattering parameters have confirmed the practicability of the simulation methodology. The fly-by structure is found to be crucial and thinner transmission lines around the Synchronous Dynamic Random Memory (SDRAM) region should be employed for achieving impedance matching with suitable design graph constructed accordingly. Finally, the effects of these models on the eye diagram are simulated to access their significance, for which the fly-by design is found to be the most critical, followed in order by package connections, via transitions, serpentine delay lines, and bends.