The Future of CMOS Scaling - Parasitics Engineering and Device Footprint Scaling

被引：3

作者：

Wong, H. -S. Philip ^{[1
]}

Wei, Lan ^{[1
]}

Deng, Jie ^{[1
]}

机构：

[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

来源：

2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 | 2008年

关键词：

D O I：

10.1109/ICSICT.2008.4734460

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch, which provides performance improvements at both the device and circuit level.

引用

页码：21 / 24

页数：4

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