Heterogeneous neuromorphic processor based on RISC-V architecture for real-time robotics tasks

被引：1
|
作者：
Zelensky, A. [1 ]
Alepko, A. [1 ,2 ]
Dubovskov, V [1 ,2 ]
Kuptsov, V [1 ]
机构：
[1] Moscow State Univ Technol STANKIN, Moscow, Russia
[2] Sci Mfg Complex Technol Ctr, Zelenograd, Russia
来源：
ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING IN DEFENSE APPLICATIONS II | 2020年 / 11543卷
关键词：
RISC-V ISA; multilayer perceptron; neural networks; FPGA; neuro accelerator; heterogeneous system;
D O I：
10.1117/12.2574470
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The article discusses a heterogeneous processor based on an open source 64-bit core of the RISC-V architecture, combined with a reconfigurable neural network accelerator. The features of the implementation of a binary matrix neural network on FPGA and its combination with the RISC-V RV64GC core in tasks of cognitive robotics and industrial production are investigated in order to increase safety in the interaction of a robot and a person.
引用
收藏
页数：8
相关论文
共 50 条
  • [31] A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions
    Du, Peiran
    Cai, Zhaohui
    ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, ICA3PP 2023, PT I, 2024, 14487 : 439 - 454
  • [32] Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time Systems
    Nurmi, Antti
    Lindgren, Per
    Kalache, Abdesattar
    Lunnikivi, Henri
    Hamalainen, Timo D.
    ARCHITECTURE OF COMPUTING SYSTEMS, ARCS 2024, 2024, 14842 : 316 - 330
  • [33] RISC PROCESSOR ENTERS THE RACE OF REAL-TIME COMPUTING
    WILSON, R
    COMPUTER DESIGN, 1987, 26 (22): : 23 - 24
  • [34] Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
    Kuo, Yao-Ming
    Flanagan, Mark F.
    Garcia-Herrero, Francisco
    Ruano, Oscar
    Antonio Maestro, Juan
    IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 2023, 59 (05) : 5835 - 5846
  • [35] RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement
    Spang, Christoph
    Meisel, Florian
    Koch, Andreas
    EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, SAMOS 2021, 2022, 13227 : 179 - 194
  • [36] VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture
    Xin, Guozhu
    Han, Jun
    Yin, Tianyu
    Zhou, Yuchao
    Yang, Jianwei
    Cheng, Xu
    Zeng, Xiaoyang
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (08) : 2672 - 2684
  • [37] Neuromorphic processor for real-time biosonar object detection
    Cauwenberghs, G
    Edwards, RT
    Deng, YB
    Genov, R
    Lemonds, D
    2002 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-IV, PROCEEDINGS, 2002, : 3984 - 3987
  • [38] RISC-V FPGA Platform toward ROS-based Robotics Application
    Lee, Jaewon
    Chen, Hanning
    Young, Jeffrey
    Kim, Hyesoon
    2020 30TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2020, : 370 - 370
  • [39] RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism
    Wang, Zhou
    Du, Haochen
    Han, Baoyi
    Xu, Yanqing
    Tang, Xiaonan
    Zhou, Yang
    Zheng, Zhe
    Cui, Wenpeng
    Xiong, Yanwei
    Wei, Shaojun
    Qiao, Shushan
    Yin, Shouyi
    2024 IEEE 6TH INTERNATIONAL CONFERENCE ON AI CIRCUITS AND SYSTEMS, AICAS 2024, 2024, : 302 - 306
  • [40] AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors
    Kamaleldin, Ahmed
    Goehringer, Diana
    IEEE ACCESS, 2022, 10 : 43895 - 43913
12345