Interconnect Customization for a Hardware Fabric

被引:5
|
作者
Mehta, Gayatri [1 ]
Stander, Justin
Baz, Mustafa
Hunsaker, Brady
Jones, Alex K. [1 ]
机构
[1] Univ Pittsburgh, Dept Elect & Comp Engn, Pittsburgh, PA 15261 USA
关键词
Design; Experimentation; Standardization; Verification; Reconfigurable; hardware fabric; low-energy; computer-aided design; architecture; demonstrable;
D O I
10.1145/1455229.1455240
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article describes several multiplexer-based interconnection strategies designed to improve energy consumption of stripe-based coarse-grain reconfigurable fabrics. Application requirements for the architecture as well as two dense subgraphs are extracted from a suite of signal and image processing benchmarks. These statistics are used to drive the strategy of the composition of multiplexer-based interconnect. The article compares interconnects that are fully connected between stripes, those with a cardinality of 8: 1 to 4: 1, and extensions that provide a 5: 1 cardinality, limited 6: 1 cardinality, and hybrids between 5: 1 and 3: 1 cardinalities. Additionally, dedicated vertical routes are considered replacing some computational units with dedicated pass-gates. Using a fabric interconnect model (FIM) written in XML, we demonstrate that fabric instances and mappers can be automatically generated using a Web-based design flow. Upon testing these instances, we found that using an 8: 1 cardinality interconnect with 33% of the computational units replaced with dedicated pass-gates provided the best energy versus mappability tradeoff, resulting in a 50% energy improvement over fully connected rows and 20% energy improvement over an 8: 1 cardinality interconnect without dedicated vertical routes.
引用
收藏
页数:32
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