Optimization of source/drain extension for robust speed performance to process variation in undoped double-gate CMOS

被引：0

作者：

Yang, Ji-Woon ^{[1
]}

Pham, Daniel ^{[2
]}

Zeitzoff, Peter ^{[1
]}

Huff, Howard ^{[1
]}

Brown, George ^{[1
]}

机构：

[1] SEMATECH, 2706 Montopolis Dr, Austin, TX 78741 USA

[2] Freescale Assignee, Austin, TX 78741 USA

来源：

2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The speed performance of undoped double-gate CMOS with a gate-source/drain underlap structure is investigated using a 2D device and compact model simulation. The gate-source/drain underlap structure yields optimal characteristics and shows robustness to process variation when the structure is optimized.

引用

页码：48 / +

页数：2

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