Low-power driven logic synthesis using accurate power estimation technique

With the increasing use of portable computing and wireless communication systems, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Towards this end, we introduce algebraic procedures for node extraction and factorization that target low power consumption in combinational logic circuits. New cost function is also proposed for the sum-of-products representation of the expressions. The's cost function is used to guide the power optimization procedures. The spatial and temporal correlations of signals were taken into account to gain accurate power estimation. The results show that an average of 10% saving was gained in pourer using logic synthesis with the proposed accurate power estimation technique, compared to area optimized designs. Results also show that the power dissipation of the circuit, synthesized assuming temporally uncorrelated primary inputs, can dissipate 75% more power than that of the circuits assuming temporally correlated inputs.