New trends in wafer level packaging

被引：3

作者：

Sillon, N. ^{[1
]}

Henry, D. ^{[1
]}

Souriau, J-C ^{[1
]}

Brun, J. ^{[1
]}

Boutry, H. ^{[1
]}

Cheramy, S. ^{[1
]}

机构：

[1] CEA Leti Minatec, Grenoble, France

来源：

PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2009年

关键词：

D O I：

10.1109/IITC.2009.5090390

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present in this paper the two generic integration schemes developed at Leti, aiming to address two opposite industrial needs. The first scheme, based on TSV free Via Belt technology, allows wafer level integration of highly heterogeneous systems taking into account different technologies, wafer and die sizes and mainly targets end-user companies looking for generic technologies. The second one, based on TSV WLP and active silicon interposer, mainly addresses the IDMs needs. Main technological bricks related to both schemes are presented and validated through specific demonstrators.

引用

页码：211 / 213

页数：3

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