Low-temperature poly-Si thin-film transistor with a N2O-plasma ONO multilayer gate dielectric

被引:6
|
作者
Chang, KM [1 ]
Yang, WC
Hung, BF
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan
[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan
关键词
D O I
10.1149/1.1753253
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with oxide/nitride/oxynitride (ONO) multilayer gate dielectrics were fabricated. The low-temperature (less than or equal to300degreesC) ONO multilayer dielectric uses three stacked layers: the bottom layer is a very thin N2O-plasma oxynitride deposited by plasma-enhanced chemical vapor deposition (PECVD), the middle layer is PECVD Si3N4, and the top layer is tetraethoxysilane (TEOS) oxide. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time-dependent dielectric breakdown lifetime and a lower charge trapping rate than single-layer PECVD TEOS oxide or nitride. The fabricated poly-Si TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 213 cm(2)/V s, and an ON/OFF current ratio of over 10(8). (C) 2004 The Electrochemical Society.
引用
收藏
页码:G148 / G150
页数:3
相关论文
共 50 条
  • [21] Gate capacitance characteristics of a poly-Si thin film transistor
    Bindra, S
    Haldar, S
    Gupta, RS
    SOLID-STATE ELECTRONICS, 2004, 48 (05) : 675 - 681
  • [22] EFFECTS OF F+ IMPLANTATION ON THE CHARACTERISTICS OF POLY-SI FILMS AND LOW-TEMPERATURE N-CH POLY-SI THIN-FILM TRANSISTORS
    PARK, JW
    AHN, BT
    LEE, K
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1995, 34 (03): : 1436 - 1441
  • [23] Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors
    Chen, Chih-Yang
    Wang, Tong-Yi
    Ma, Ming-Wen
    Chen, Wei-Cheng
    Lin, Hsiao-Yi
    Yeh, Kuan-Lin
    Wang, Shen-De
    Lei, Tan-Fu
    AD'07: Proceedings of Asia Display 2007, Vols 1 and 2, 2007, : 1233 - 1237
  • [24] Inverted staggered poly-Si thin-film transistor with planarized SOG gate insulator
    Cheon, Jun Hyuk
    Bae, Jung Ho
    Jang, Jin
    IEEE ELECTRON DEVICE LETTERS, 2008, 29 (03) : 235 - 237
  • [25] An offset-compensated LVDS receiver with low-temperature poly-si thin film transistor
    Min, Kyungyoul
    Yoo, Changsik
    ETRI JOURNAL, 2007, 29 (01) : 45 - 49
  • [26] Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization
    Samsung Electronics Co, Ltd, Kyungki-Do, Korea, Republic of
    IEEE Electron Device Lett, 4 (160-162):
  • [27] FABRICATION OF A POLY-SI THIN-FILM TRANSISTOR WITH STORAGE CAPACITOR
    MIMURA, A
    KIMURA, E
    SUZUKI, T
    ONO, K
    OHWADA, JI
    KONISHI, N
    MIYATA, K
    DISPLAYS, 1991, 12 (3-4) : 141 - 146
  • [28] Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization
    Lee, SW
    Joo, SK
    IEEE ELECTRON DEVICE LETTERS, 1996, 17 (04) : 160 - 162
  • [29] A high performance thin-film transistor using a low temperature poly-Si by silicide mediated crystallization
    Kwak, WK
    Cho, BR
    Yoon, SY
    Park, SJ
    Jang, J
    IEEE ELECTRON DEVICE LETTERS, 2000, 21 (03) : 107 - 109
  • [30] A new poly-Si thin-film transistor with poly-Si/a-Si double active layer
    Park, KC
    Choi, KY
    Yoo, JS
    Han, MK
    IEEE ELECTRON DEVICE LETTERS, 2000, 21 (10) : 488 - 490