Diagnostic test generation for arbitrary faults

被引:0
|
作者
Bhatti, Naresh K. [1 ]
Blanton, R. D. [1 ]
机构
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, 5000 Forbes Ave, Pittsburgh, PA 15213 USA
来源
2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2 | 2006年
关键词
fault diagnosis; VLSI testing; ATPG;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
It is now generally accepted that the stuck-at fault model is no longer sufficient for many manufacturing test activities. Consequently, diagnostic test pattern generation based solely on distinguishing stuck-at faults is unlikely to achieve the resolution required for emerging fault types. In this work we describe a new diagnostic ATPG implementation that uses a generalized fault model. It can be easily used in arty diagnosis framework to refine diagnostic resolution for complex defects. For various types of faults that include, for example, bridge, transition, and transistor stuck-open, we show that diagnostic resolution can be significantly enhanced over a traditional diagnostic test set aimed only at stuck-at faults. Finally, we illustrate the use of our diagnostic ATPG to distinguish faults derived from a state-of-the-art diagnosis flow based on layout.
引用
收藏
页码:559 / +
页数:4
相关论文
共 50 条
  • [21] A Diagnostic Test Generation System
    Zhang, Yu
    Agrawal, Vishwani D.
    INTERNATIONAL TEST CONFERENCE 2010, 2010,
  • [22] Diagnostic Test Generation That Addresses Diagnostic Holes
    Pomeranz, Irith
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 38 (02) : 335 - 344
  • [23] Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults
    Wang, Peikun
    Gharehbaghi, Amir Masoud
    Fujita, Masahiro
    PROCEEDINGS OF THE 2019 20TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2019, : 284 - 290
  • [24] Test and Diagnosis Pattern Generation for Dynamic Bridging Faults and Transition Delay Faults
    Wu, Cheng-Hung
    Lee, Saint James
    Lee, Kuen-Jong
    2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2016, : 755 - 760
  • [25] Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults
    Mohan N.
    Anita J.P.
    Integration, 2022, 83 : 24 - 32
  • [26] Single diagnostic tests for inversion faults of gates in circuits over arbitrary bases
    Liubich, Il'ya G.
    Romanov, Dmitriy S.
    DISCRETE MATHEMATICS AND APPLICATIONS, 2022, 32 (01): : 1 - 9
  • [27] Fault Simulation and Test Generation for Clock Delay Faults
    Higami, Yoshinobu
    Takahashi, Hiroshi
    Kobayashi, Shin-ya
    Saluja, Kewal K.
    2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [28] Automatic test pattern generation for resistive bridging faults
    Engelke, P
    Polian, I
    Renovell, M
    Becker, B
    DBT 2004: PROCEEDINGS OF THE 2004 IEEE INTERNATIONAL WORKSHOP ON CURRENT & DEFECT BASED TESTING, 2004, : 91 - 96
  • [29] Automatic Test Pattern Generation for Resistive Bridging Faults
    Piet Engelke
    Ilia Polian
    Michel Renovell
    Bernd Becker
    Journal of Electronic Testing, 2006, 22 : 61 - 69
  • [30] Test Generation for Open and Delay Faults in CMOS Circuits
    Wu, Cheng-Hung
    Lee, Kuen-Jong
    Reddy, Sudhakar M.
    2017 INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA), 2017, : 21 - 26