Advanced Nano CMOS using Ge/III-V semiconductors for Low Power Logic LSIs

被引：0

作者：

Takagi, Shinichi ^{[1
]}

Takenaka, Mitsuru

机构：

[1] Univ Tokyo, Dept Elect Engn & Informat Syst, Sch Engn, Tokyo, Japan

来源：

2015 IEEE 15TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2015年

关键词：

MOSFET; Tunneling FET; Germanium; III-V semiconductors; Metal-Oxide-Semiconductor; Mobility; Interface states; FIELD-EFFECT TRANSISTORS; N-MOSFETS; SI; MOBILITY; S/D;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. In addition, Tunneling-FET (TFET) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. Thus, the establishment of the device/process/integration technologies of Ge/III-V MOSFETs and TFETs for satisfying those device requirements is of the paramount importance. In this paper, we address channel, source/drain (S/D) and gate stack engineering for realizing these devices with emphasis on thin EOT and ultrathin body structures, which are mandatory in the future technology nodes.

引用

页码：654 / 658

页数：5

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