Advanced Nano CMOS using Ge/III-V semiconductors for Low Power Logic LSIs

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. In addition, Tunneling-FET (TFET) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. Thus, the establishment of the device/process/integration technologies of Ge/III-V MOSFETs and TFETs for satisfying those device requirements is of the paramount importance. In this paper, we address channel, source/drain (S/D) and gate stack engineering for realizing these devices with emphasis on thin EOT and ultrathin body structures, which are mandatory in the future technology nodes.