III-V and Ge/strained SOI tunneling FET technologies for low power LSIs

被引：0
|
作者：
Takagi, S. [1 ,2 ]
Kim, M. [1 ,2 ]
Noguchi, M. [1 ]
Ji, S. -M. [1 ,2 ]
Nishi, K. [1 ,2 ]
Takenaka, M. [1 ,2 ]
机构：
[1] Univ Tokyo, Dept Elect Engn & Informat Syst, Bunkyo Ku, 7-3-1 Hongo, Tokyo 1138656, Japan
[2] CREST, JST, Bunkyo Ku, Tokyo 1138656, Japan
来源：
2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY) | 2015年
关键词：
D O I：
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high I-on/I-off ratio over 10(7) and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that I-on and SS are improved by positive back bias. We have also demonstrated the operation of high I-on/I-off and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p(+)/n source junctions. The small S.S. of 64 mV/dec and large I-on/I-off ratio over 10(6) have been realized in the planar-type III-V TFETs.
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页数：2
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