III-V and Ge/strained SOI tunneling FET technologies for low power LSIs

We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/III-V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high I-on/I-off ratio over 10(7) and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found that I-on and SS are improved by positive back bias. We have also demonstrated the operation of high I-on/I-off and low SS planar-type InGaAs Tunnel FETs with Zn-diffused source junctions. Solid-phase Zn diffusion can realize steep-profile and defect-less p(+)/n source junctions. The small S.S. of 64 mV/dec and large I-on/I-off ratio over 10(6) have been realized in the planar-type III-V TFETs.