Performance driven synthesis for pass-transistor logic

Far many digital designs, implementation in pass-transistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics to static CMOS. Binary Decision Diagrams (BDDs) have been used for PTL synthesis because of the close relationship between BDDs and Pm. Thus far; BDD optimization for PTL synthesis has targeted minimizing the number of BDD nodes. This strategy leads to smaller PTL implementations, brit it carl result irt circuits of poor performance. In this paper; we model the delay of PTL circuits derived from BDDs, and propose procedures to reduce the worst-case delay or the area-delay product of such circuits. The experimental results show a significant improvement in the delay (30%) or area-delay product (24%) for the ISCAS benchmark circuits.