ELECTRICAL RELIABILITY OF Cu/Sn MICRO-BUMP IN WAFER LEVEL PACKAGING FOR BioMEMS DEVICES

被引:0
|
作者
Jeong, Myeong-Hyeok [1 ]
Kim, Jae-Won [1 ]
Kwak, Byung-Hyun [1 ]
Park, Young-Bae [1 ]
Kim, Byoung-Joon [2 ]
Joo, Young-Chang [2 ]
机构
[1] Andong Natl Univ, Sch Mat Sci & Engn, Andong 760749, South Korea
[2] Seoul Natl Univ, Dept Mat Sci & Engn, Seoul 151744, South Korea
来源
关键词
Cu/Sn micro-bump; Electromigration; Wafer Level Packaging; BioMEMS Devices; ELECTROMIGRATION;
D O I
暂无
中图分类号
R318 [生物医学工程];
学科分类号
0831 ;
摘要
The electrical reliability of Cu/Sn micro-bump in wafer level packaging for advanced BioMEMS devices applications were systematically investigated during current stressing condition. After bump bonding, Cu3Sn and Cu6Sn5 intemietallic phases were observed, and Cu3Sn formed and grew at Cu pillar/Cu6Sn5 interface with increasing annealing and current stressing time. The kinetics of intermetallic compound growth changed when all Sn in Cu/Sn micro-bump was exhausted. The complete consumption time of Sn phase in electromigration condition was faster than that in annealing condition. Under current stressing condition, intermetallic compound growth was significantly enhanced by current stressing where the growth rate follows a linear relationship with stressing time.
引用
收藏
页码:311 / +
页数:2
相关论文
共 50 条
  • [21] 300 mm wafer stepper for bump and wafer level scale packaging (CSP) applications
    Kay, S
    Anberg, D
    PAN PACIFIC MICROELECTRONICS SYMPOSIUM, 2001, PROCEEDINGS, 2001, : 182 - 189
  • [22] Research on the reliability of Cu/Sn copper pillar bump
    Zhao, Wen
    Rao, Li
    Hu, Anmin
    Gao, Liming
    Li, Ming
    2017 18TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2017, : 946 - 949
  • [23] Wafer level hermetic packaging based on electroplating Cu-Sn alloy films
    Du, Li-Dong, 1600, Chinese Academy of Sciences (22):
  • [24] Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology
    Cao Yuhan
    Luo Le
    JOURNAL OF SEMICONDUCTORS, 2009, 30 (08)
  • [25] RESIDUAL STRESS IN SILICON CAUSED BY CU-SN WAFER-LEVEL PACKAGING
    Taklo, Maaike. M. V.
    Vardoy, Astrid-Sofie
    De Wolf, Ingrid
    Simons, Veerle
    van de Wiel, H. J.
    van der Waal, Adri
    Lapadatu, Adriana
    Martinsen, Stian
    Wunderle, Bernhard
    PROCEEDINGS OF THE ASME INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2013, VOL 1, 2014,
  • [26] Cavityless wafer level packaging of SAW devices
    Bhattacharjee, K.
    Shvetsov, A.
    Zhgoon, S.
    2007 IEEE ULTRASONICS SYMPOSIUM PROCEEDINGS, VOLS 1-6, 2007, : 1886 - +
  • [27] Wafer Level Hermetic Packaging of MOEMS Devices
    Yang, Charles
    Xu, Antai
    Wang, Ye
    32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium, 2007, : 182 - 185
  • [28] Design Study of the Bump on Flexible Lead by FEA for Wafer Level Packaging
    Eidner, I.
    Wunderle, B.
    Pan, K. L.
    Wolf, M. J.
    Ehrmann, O.
    Reichl, H.
    EUROSIME 2009: THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICRO-ELECTRONICS AND MICRO-SYSTEMS, 2009, : 348 - +
  • [29] Investigation on Solder Bump Process Polyimide Cracking for wafer level packaging
    Shi, Lei
    Chen, Lin
    Zhang, David Wei
    Liu, Evan
    Huang, Jin-Xin
    2016 17TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2016, : 1140 - 1145
  • [30] Retarding the Cu-Sn and Ag-Sn intermetallic compounds by applying Cu-xZn alloy on micro-bump in novel 3D-IC technologies
    Chen, Wei-Yu
    Chou, Tzu-Ting
    Tu, Wei
    Chang, Hsiang-Ching
    Lee, Christine Jill
    Duh, Jenq-Gong
    JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 2015, 26 (04) : 2357 - 2362