Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Packaging Technology for Multi-Chip and 3D System Integration

The demand for miniaturized package size, higher performance and integration density, lower power consumption, and lower manufacturing cost drives the development of various new packaging technologies, such as WLP, 2.5D interposer, 3D WLCSP etc. Recently, Fan-Out Wafer Level Package (FOWLP) has aroused more and more interest since it emerged as a successful technology in providing the solution to meet advanced system packaging and integration requirements. FOWLP has also become a key-enabling technology for multi-chip and 3D system integration. Embedded silicon fan-out (eSiFO (R)) technology developed by Huatian group was a low cost FOWLP technology, which eliminates molding, temporary bonding and de-bonding in the process flow. The eSiFO (R) technology for single chip with a high yield of 99.5% was reported. In this paper, the development of eSiFO (R) technology for multi-chip and 3D system integration was reported. One package in the size of 5.2x4.0 mm(2) and containing 5 chips has been successfully produced. Small warpage of similar to 1mm for eSiFO (R) 300mm wafer was achieved even with 2 layer thick RDLs. Another 3D-Integration package based on the eSiFO (R) technology has also been successfully demonstrated, where two dies were stacked on the top of the eSiFO (R) wafer by die placement and mass reflow processes. For the 3D eSiFO (R) SiP package, the size and thickness was 4.1x4.1mm, and 0.375 mm respectively. One RDL was formed on both front and backside of the eSiFO (R). The interconnection between the embedded chip and the stacked chips was made through micro bumps and through-silicon vias (TSVs) located in the fan-out area of the carrier wafer. The manufactured packages have shown good electrical yield and passed standard reliability tests.