Improving Reliability in Application-Specific 3D Network-on-Chip

Three-dimensional integrated circuits (3D ICs) offer an attractive solution for overcoming the barriers to interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology, with smaller form factor, higher integration density, and the support for the realization of mixed-technology chips. As feature sizes shrink, faults occur in on-chip network become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of router failures by means of designing fault-tolerant architecture. The proposed architecture not only is able to recover from routers failure, but also improves the average response time of the system. In this design, in order to avoid adding a port in a router, a new component is also developed to reduce hardware overhead.