Low-power area-efficient decimation filters in sigma-delta ADCs

被引：0

作者：

Yi, Feng ^{[1
]}

Wu, Xiaobo ^{[1
]}

Xu, Jian ^{[1
]}

机构：

[1] Zhejiang Univ, Inst VLSI Design, Hangzhou 310027, Peoples R China

来源：

EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The performances of different structures for Sinc filters were analyzed and compared in this paper. To reduce their power consumption and chip area, a new optimum method was proposed. And it was implemented in poly-phase structure and direct-realization structure respectively for verification. In addition, the low-power area-efficient optimization scheme for decimation filters in Sigma-Delta ADCs was also discussed. All simulation results were obtained under supply voltage of 1.62 V using TSMC 0.18 mu m CMOS technology. The results showed that, compared to CIC, 36% area and 50% power were saved for poly-phase structure and 64% power consumption was reduced for direct-realization structure.

引用

页码：833 / 836

页数：4

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