Study of Process Variations on ft in 30 nm Gate Length FinFET Using TCAD Simulations

被引：0
|
作者：
Lakshmi, B. [1 ]
Srinivasan, R. [1 ]
机构：
[1] SSN Coll Engn, Dept Informat Technol, Madras, Tamil Nadu, India
来源：
COMPUTER NETWORKS AND INFORMATION TECHNOLOGIES | 2011年 / 142卷
关键词：
f(t); FinFET; sensitivity; process variations; TCAD;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper investigates the effect of process variations on unity gain frequency (f(t)) in 30 nm gate length FinFET by performing extensive 3D TCAD simulations. TCAD tools are used to study device sensitivities on process variations. Sensitivity of f(t) on five different process parameters is studied. It is found that f(t) is more sensitive to gate length, underlap and corner radius, and less sensitive to hardmask height. Sensitivity of f(t) to fin width depends upon channel doping levels.
引用
收藏
页码：482 / 486
页数：5
相关论文
共 50 条
  • [1] Validation of 30 nm process simulation using 3D TCAD for FinFET devices
    Nawaz, Muhammad
    Molzer, Wolfgang
    Haibach, Patrick
    Landgraf, Erhard
    Roesner, Wolfgang
    Staedele, Martin
    Luyken, Hannes
    Gencer, Alp
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2006, 21 (08) : 1111 - 1120
  • [2] Simulation of self-heating effects in 30nm gate length FinFET
    Braccioli, M.
    Curatola, G.
    Yang, Y.
    Sangiorgi, E.
    Fiegna, C.
    ULIS 2008: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON, 2008, : 71 - +
  • [3] FinFET scaling to 10nm gate length
    Yu, B
    Chang, LL
    Ahmed, S
    Wang, HH
    Bell, S
    Yang, CY
    Tabery, C
    Ho, C
    Xiang, Q
    King, TJ
    Bokor, J
    Hu, CM
    Lin, MR
    Kyser, D
    INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 251 - 254
  • [4] Analysis of Multifin n-FinFET for Analog Performance at 30nm Gate Length
    Sonkusare, Reena S.
    Rathod, S. S.
    PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES), 2016, : 277 - 283
  • [5] Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length
    Kaur, Navneet
    Gill, Sandeep Singh
    Kaur, Prabhjot
    SILICON, 2022, 14 (16) : 10989 - 11000
  • [6] Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length
    Navneet Kaur
    Sandeep Singh Gill
    Prabhjot Kaur
    Silicon, 2022, 14 : 10989 - 11000
  • [7] Simulation Study on NMOS Gate Length Variation Using TCAD Tool
    Sanudin, Rahmat
    Sulong, Muhammad Suhaimi
    Morsin, Marlia
    Wahab, Mohd Helmy Abd
    2009 1ST ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2009, : 276 - 279
  • [8] Design and Simulation of 22nm FinFET Structure Using TCAD
    Kalaivani, R.
    Pravin, J. Charles
    Kumar, S. Ashok
    Sridevi, R.
    2020 5TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS' 20), 2020, : 286 - 289
  • [9] Impact of encroaching length and taper on double gate tunnel FET performance using TCAD simulations
    Sugi, S.Shinly Swarna
    Nagarajan, K.K.
    Srinivasan, R.
    Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2013, 2013, : 942 - 947
  • [10] Impact of Encroaching Length and Taper on Double Gate Tunnel FET Performance Using TCAD Simulations
    Sugi, S. Shinly Swarna
    Nagarajan, K. K.
    Srinivasan, R.
    PROCEEDINGS OF 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2013), 2013, : 942 - 947
12345