共 50 条
- [22] Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 739 - 742
- [23] Nanoscale Three-Independent-Gate Transistors: Geometric TCAD Simulations at the 10 nm-Node 2019 IEEE 14TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), 2019,
- [24] In-depth study of strained SGOI nMOSFETs down to 30nm gate length PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 297 - 300
- [25] Optimum Gate Voltage search for Junctionless Tunnel FET using TCAD Simulations 2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
- [27] A study of conventional and junctionless MOSFET using TCAD Simulations 2015 5TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING & COMMUNICATION TECHNOLOGIES ACCT 2015, 2015, : 53 - 56
- [28] A Method for FinFET Intermodulation Analysis from TCAD Simulations using a Time-domain Waveform Approach 2009 INTERNATIONAL CONFERENCE ON MULTIMEDIA, SIGNAL PROCESSING AND COMMUNICATION TECHNOLOGIES, 2009, : 276 - +
- [29] TCAD modeling and simulation of sub-100nm gate length silicon and GaN based SOI MOSFETs TRANSISTOR SCALING- METHODS, MATERIALS AND MODELING, 2006, 913 : 191 - +