Study of Process Variations on ft in 30 nm Gate Length FinFET Using TCAD Simulations

被引:0
|
作者
Lakshmi, B. [1 ]
Srinivasan, R. [1 ]
机构
[1] SSN Coll Engn, Dept Informat Technol, Madras, Tamil Nadu, India
来源
COMPUTER NETWORKS AND INFORMATION TECHNOLOGIES | 2011年 / 142卷
关键词
f(t); FinFET; sensitivity; process variations; TCAD;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper investigates the effect of process variations on unity gain frequency (f(t)) in 30 nm gate length FinFET by performing extensive 3D TCAD simulations. TCAD tools are used to study device sensitivities on process variations. Sensitivity of f(t) on five different process parameters is studied. It is found that f(t) is more sensitive to gate length, underlap and corner radius, and less sensitive to hardmask height. Sensitivity of f(t) to fin width depends upon channel doping levels.
引用
收藏
页码:482 / 486
页数:5
相关论文
共 50 条
  • [31] Corner Effects in SOI-Tri gate FinFET structure by using 3D Process and Device Simulations
    Kumar, M. Pavan
    Gupta, Santosh Kr.
    Paul, Madhumita
    PROCEEDINGS OF 2010 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGY, VOL 9 (ICCSIT 2010), 2010, : 704 - 707
  • [32] Process development for 30 nm poly gate patterning on 1.2 nm oxide.
    Heitzmann, M
    Nier, ME
    MICROELECTRONIC ENGINEERING, 2000, 53 (1-4) : 159 - 162
  • [33] 16 nm FinFET Based Radiation Hardened Standard Cell Library Analysis Using Visual TCAD Tool
    Grace, Jessy
    Bhushan, Sphoorthy
    Rao, Chinnam S. V. Maruthi
    Chavan, Ameet
    Advances in Intelligent Systems and Computing, 2021, 1350 AISC : 206 - 213
  • [34] Impact of BOX scaling on 30 nm gate length FD SOI MOSFETs
    Fujiwara, M
    Morooka, T
    Yasutake, N
    Ohuchi, K
    Aoki, N
    Tanimoto, H
    Kondo, M
    Miyano, K
    Inaba, S
    Ishimaru, K
    Ishiuchi, H
    2005 IEEE International SOI Conference, Proceedings, 2005, : 180 - 182
  • [35] Transistor operations in 30-nm-gate-length EJ-MOSFETs
    Kawaura, H
    Sakamoto, T
    Baba, T
    Ochiai, Y
    Fujita, J
    Matsui, S
    Sone, J
    55TH ANNUAL DEVICE RESEARCH CONFERENCE, DIGEST - 1997, 1997, : 14 - 15
  • [36] Exploration and analysis of n-FinFET implementing stacked high-K at 08 nm gate length
    Nanda, Swagat
    Kumari, Sapna
    Dhar, Rudra Sankar
    SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 2023, 49 (01):
  • [37] Exploration and analysis of n-FinFET implementing stacked high-K at 08 nm gate length
    Swagat Nanda
    Sapna Kumari
    Rudra Sankar Dhar
    Sādhanā, 49
  • [38] Sub-20 nm Gate Length FinFET Design: Can High-κ Spacers Make a Difference?
    Sachid, Angada B.
    Francis, Roswald
    Baghini, Maryam Shojaei
    Sharma, Dinesh K.
    Bach, Karl-Heinz
    Mahnkopf, Reinhard
    Rao, V. Ramgopal
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 697 - +
  • [39] Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process
    Chatterjee, A
    Chapman, RA
    Dixit, G
    Kuehne, J
    Hattangady, S
    Yang, H
    Brown, GA
    Aggarwal, R
    Erdogan, U
    He, Q
    Hanratty, M
    Rogers, D
    Murtaza, S
    Fang, SJ
    Kraft, R
    Rotondaro, ALP
    Hu, JC
    Terry, M
    Lee, W
    Fernando, C
    Konecni, A
    Wells, G
    Frystak, D
    Bowen, C
    Rodder, M
    Chen, IC
    INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, : 821 - 824
  • [40] Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability
    Seoane, Natalia
    Indalecio, Guillermo
    Nagy, Daniel
    Kalna, Karol
    Garcia-Loureiro, Antonio J.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (02) : 456 - 462