DEVELOPMENT OF THE LDPC CODER-DECODER OF THE DVB-S2 STANDARD ON FPGA

被引：0

作者：

Zinchenko, M. Yu. ^{[1
]}

Levadniy, A. M. ^{[1
]}

Grebenko, Yu. A. ^{[1
]}

机构：

[1] Natl Res Univ MPEI, Moscow, Russia

来源：

2018 SYSTEMS OF SIGNAL SYNCHRONIZATION, GENERATING AND PROCESSING IN TELECOMMUNICATIONS (SYNCHROINFO) | 2018年

关键词：

FEC; decoder; LDPC; DVB-S2; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Forward error correction (FEC) is a mandatory step in the processing of information in modern digital communication channels. Encoding methods are constantly improved. Today's most popular FEC codes are low-density parity check codes (LDPC). The paper presents the results of the development on the FPGA the encoder and the decoder of LDPC codes compatible with the standard DVB-S2. Parametrized FE. modules with the ability to use several coding rates and two frames types of the standard were developed. In this paper, proposed architectures of coder and decoder, methods for improving performance and used resources of FPGA are presented.

引用

页数：3

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