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- [47] Thermal-Electrical Co-simulation for Wafer-level Chip Scale Package Maximum Bearing Current EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 860 - 863
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- [49] A Hardware/Software Co-simulation Approach for Power Converter Firmware Design and Debugging 2017 AUSTRALASIAN UNIVERSITIES POWER ENGINEERING CONFERENCE (AUPEC), 2017,
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