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- [12] Modeling and Co-Simulation of I/O Interconnects for On-Chip and Off-Chip EMI Prediction 2012 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2012, : 821 - 824
- [13] Off-chip decoupling capacitor allocation for chip package co-designa 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2007, : 618 - +
- [14] Modeling Methodologies for Multi Level PCB-Package Co-Simulation & Co-Design 2013 IEEE 22ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2013, : 57 - 57
- [15] Design a co-simulation platform for power system and communication network 2014 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS (SMC), 2014, : 3036 - 3041
- [17] Co-simulation of AC Power Noise of CMOS Microprocessor using Capacitor Charging Modeling 2012 2ND IEEE CPMT SYMPOSIUM JAPAN, 2012,
- [18] Co-simulation and Co-design of Chip-Package-Board Interfaces in Highly- Integrated RF Systems 2016 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), 2016, : 94 - 101
- [19] Chip-Package Co-Design Methodology for Global Co-Simulation of Re-Distribution Layers (RDL) 2008 IEEE-EPEP ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2008, : 53 - +
- [20] Transient Electrical-Thermal Co-Simulation in the Design of On-Chip and 3-D Interconnects 2015 31st International Review of Progress in Applied Computational Electromagnetics (ACES) Vol 31, 2015,