Low power, high speed, charge recycling CMOS threshold logic gate

被引：36
|
作者：
Celinski, P
López, JF
Al-Sarawi, S
Abbott, D
机构：
[1] Univ Adelaide, Dept Elect & Elect Engn, Ctr High Performance Integrated Technol & Syst, Adelaide, SA 5005, Australia
[2] Univ Las Palmas G C, Res Inst Appl Microelect, Las Palmas Gran Canaria 35017, Spain
来源：
ELECTRONICS LETTERS | 2001年 / 37卷 / 17期
关键词：
D O I：
10.1049/el:20010742
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.
引用
收藏
页码：1067 / 1069
页数：3
相关论文
共 50 条
  • [41] Design methodology of a low power high speed CMOS ADC
    Maman, N
    Jharia, B
    Agarwal, RP
    PROCEEDINGS OF THE IEEE INDICON 2004, 2004, : 530 - 533
  • [42] Low-power super-threshold FinFET domino logic circuits for high-speed applications
    Bo, Hong
    Jianping, Hu
    Dongmei, Li
    Chenghao, Han
    Open Automation and Control Systems Journal, 2014, 6 (01): : 907 - 912
  • [43] NOVEL ULTRA LOW-VOLTAGE AND HIGH SPEED DOMINO CMOS LOGIC
    Berg, Y.
    PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP, 2010, : 225 - 228
  • [44] An improved high speed, and low voltage CMOS current mode logic latch
    Oscar Lozada
    Guillermo Espinosa
    Analog Integrated Circuits and Signal Processing, 2017, 90 : 247 - 252
  • [45] An improved high speed, and low voltage CMOS current mode logic latch
    Lozada, Oscar
    Espinosa, Guillermo
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 90 (01) : 247 - 252
  • [46] HIGH-SPEED THRESHOLD GATE MULTIPLIER
    KENT, SA
    IEEE TRANSACTIONS ON COMPUTERS, 1977, 26 (12) : 1279 - 1283
  • [47] 45nm gate length bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications
    Yang, CK
    Chen, TF
    Liang, CS
    Chen, TJ
    Chang, TC
    Cheng, LW
    Lin, HS
    Li, G
    Wu, DY
    Chen, JK
    Chien, SC
    Sun, SW
    Cheek, J
    Michael, M
    Wu, D
    Fisher, P
    Wristers, D
    ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 415 - 418
  • [48] High performance low power CMOS dynamic logic for arithmetic circuits
    Navarro-Botello, Victor
    Montiel-Nelson, Juan A.
    Nooshabadi, Saeid
    MICROELECTRONICS JOURNAL, 2007, 38 (4-5) : 482 - 488
  • [49] A highly manufacturable low power and high speed HfSiO CMOS FET - with dual poly-Si gate electrodes
    Iwamoto, T
    Ogura, T
    Terai, M
    Watanabe, H
    Watanabe, H
    Ikarashi, N
    Miyamura, M
    Tatsumi, T
    Saitoh, M
    Morioka, A
    Watanabe, K
    Saito, Y
    Yabe, Y
    Ikarashi, T
    Masuzaki, K
    Mochizuki, Y
    Mogami, T
    2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 639 - 642
  • [50] Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits
    Srivastava, A
    MICROELECTRONICS RELIABILITY, 2000, 40 (12) : 2107 - 2110
12345