Low power, high speed, charge recycling CMOS threshold logic gate

被引：36
|
作者：
Celinski, P
López, JF
Al-Sarawi, S
Abbott, D
机构：
[1] Univ Adelaide, Dept Elect & Elect Engn, Ctr High Performance Integrated Technol & Syst, Adelaide, SA 5005, Australia
[2] Univ Las Palmas G C, Res Inst Appl Microelect, Las Palmas Gran Canaria 35017, Spain
来源：
ELECTRONICS LETTERS | 2001年 / 37卷 / 17期
关键词：
D O I：
10.1049/el:20010742
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.
引用
收藏
页码：1067 / 1069
页数：3
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