Building blocks X-FAB SOI 0.18 μm

被引：0

作者：

Cizel, J. -B. ^{[1
,3
]}

Ahmad, S. ^{[3
]}

Callier, S. ^{[2
]}

Cornat, R. ^{[1
]}

Dulucq, F. ^{[2
]}

Fleury, J. ^{[3
]}

Martin-Chassard, G. ^{[2
]}

Raux, L. ^{[2
]}

de La Taille, C. ^{[2
]}

Thienpont, D. ^{[2
]}

机构：

[1] Ecole Polytech, CNRS IN2P3, LLR, F-91128 Palaiseau, France

[2] Ecole Polytech, CNRS IN2P3, OMEGA, F-91128 Palaiseau, France

[3] WEEROC SAS, F-91400 Orsay, France

来源：

JOURNAL OF INSTRUMENTATION | 2015年 / 10卷

关键词：

Analogue electronic circuits; Calorimeters; Front-end electronics for detector readout;

D O I：

10.1088/1748-0221/10/02/C02007

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

This work has been done in order to study a new technology provided by X-FAB named xt018. It is an SOI (Silicon On Insulator) technology with a minimal gate length of 180 nm. Building blocks have been done to test the advantages and drawbacks of this technology compared to the one currently used (AMS SiGe 0.35 mu m). These building blocks have been designed to fit in an existing experience housed by the CALICE collaboration: the read-out chip for the Electromagnetic CALorimeter (ECAL) of the foreseen International Linear Collider (ILC). Performances will be compared to those of the SKIROC2 chip designed by the OMEGA laboratory, trying to fit the same r equirements. The chip is being manufactured and will be back for measurements in December, the displayed results are only simulation results and thus the conclusions concerning the performances of these building blocks are subject to change.

引用

页数：9

共 50 条

[21] Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI
Esfahani, Mohammad Nasr
Kilinc, Yasin
Karakan, M. Cagatay
Orhan, Ezgi
Hanay, M. Selim
Leblebici, Yusuf
Alaca, B. Erdem
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2018, 28 (04)
[22] High performance SRAMs IN 1.5 V, 0.18μm partially depleted SOI technology
Joshi, RV
Pellela, A
Wagner, O
Chan, YH
Dachtera, W
Wilson, S
Kowalczyk, SP
2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2002, : 74 - 77
[23] Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology
Toulon, G.
Cortes, I.
Morancho, F.
Hugonnard-Bruyere, E.
Villard, B.
Toren, W. J.
SOLID-STATE ELECTRONICS, 2011, 61 (01) : 111 - 115
[24] A 1024-Element Scalable Optical Phased Array in 0.18μm SOI CMOS
Chung, SungWon
Abediasl, Hooman
Hashemi, Hossein
2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 262 - 262
[25] A Phase Coherent 7-bit Digital Step Attenuator on 0.18μm SOI
Jarihani, Arash Ebrahimi
Kocer, Fatih
2017 12TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2017, : 167 - 170
[26] Versatile HV Lateral JFETs design in a 0.18μm SOI superjunction BCD technology
Hao, Yang
Kuniss, Uta
Kittler, Gabriel
Hoelke, Alexander
2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2013, : 143 - 146
[27] Fast-transient Capacitor-Less LDO in 0.18μm SOI Technology
Gao, Mali
Cai, Xiaowu
Gao, Yuexin
Xia, Ruirui
Li, Bo
2022 IEEE ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PRIMEASIA, 2022, : 77 - 80
[28] Generation and Propagation of Single Event Transients in 0.18-μm Fully Depleted SOI
Gouker, Pascale
Brandt, Jim
Wyatt, Peter
Tyrrell, Brian
Soares, Anthony
Knecht, Jeffrey
Keast, Craig
McMorrow, Dale
Narasimham, BalaJi
Gadlage, Matthew
Bhuva, Bharat
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, 55 (06) : 2854 - 2860
[29] OPTIMIZATION OF DEEP TRENCH ISOLATION ON 0.18μm SOI BCD TECHNOLOGY FOR AUTOMOTIVE APPLICATION
Salleh, Siti Aisah Binti Mohd
Ching, Sim Poh
CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC, 2024,
[30] 0.18 μm SOI工艺抗辐照触发器性能研究
周昕杰
于宗光
田海燕
陈嘉鹏
固体电子学研究与进展, 2014, 34 (05) : 460 - 464

← 1 2 3 4 5 →