A 39GHz Bandwidth, 2.5GS/s 7-bit SAR ADC in 22nm FDSOI CMOS

A synchronous SAR ADC lane architecture using time-interleaved comparators to drive half of the shift-register cells on alternate phases of the clock is proposed to relax the delay constraints around the SAR loop and thus maximize the sampling rate. The set-and-down capacitive DAC further increases the sampling- rate while reducing front-end loading on the input buffer stage to achieve a record analog input signal bandwidth of 39 GHz. The 7-bit SAR ADC, manufactured in 22nm FDSOI CMOS, also includes a 12.5% duty cycle, 8-phase generator featuring CMOS logic with inductive peaking which operates with input clock frequencies up to 40 GHz. The SAR ADC lane occupies 75 mu mx10 mu m and consumes 17.5 mW at 2.5 GS/s, and 19.4 mW at 3 GS/s. It achieves an ENOB of 5.18 and 4.75 at 2.5 GS/s and 3 GS/s, respectively, with SFDR greater than 34 dB over the 39 GHz input bandwidth, limited by the linearity of the input buffer.