A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI

This work presents a 600MS/s 10-bit single-channel asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) using a highly linear unit via-based delta-length capacitive digital-to-analog converter (C-DAC). The plain and regular segmented C-DAC structure is presented in detail, which provides close to 13-bit static matching with an area of only 1160 mu m(2). A Flash ADC is employed to pre-load some MSBs for improved conversion speed while also efficiently utilizing DAC segmentation, which is practically necessary in delta-length-based C-DACs. This ADC architecture can easily be extended to a time-interleaved SAR to fully take advantage of the fast Flash conversion. The ADC was fabricated in a 22nm FDSOI technology and achieves a SNDR of 51.37dB at 600MS/s with near Nyquist input while consuming 3.04mW from a 0.85V supply, which leads to a Walden FoM of 16.74fJ/conversion-step.