A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI

被引：1

作者：

Cordova, David ^{[1
,2
]}

Cops, Wim ^{[2
]}

Deval, Yann ^{[1
]}

Rivet, Francois ^{[1
]}

Lapuyade, Herve ^{[1
]}

Nodenot, Nicolas ^{[2
]}

Piccin, Yohan ^{[2
]}

机构：

[1] Univ Bordeaux, IMS Lab, Bordeaux INP, CNRS,UMR 5218, Talence, France

[2] MACOM Technol Solut, Sophia Antipolis, France

来源：

2020 IFIP/IEEE 28TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2020年

关键词：

Analog-to-digital conversion; analog-to-digital converter (ADC); low power; single channel; successive approximation register (SAR); COMPARATORS; OFFSET; SPEED;

D O I：

10.1109/VLSI-SOC46417.2020.9344084

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a very low-power 875 MS/s 7b single-channel high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a SNDR/SFDR at Nyquist rate of 41.46/55.01 dB. The use of an integer-based split CDAC combined with an improvement for the LSB capacitor allows a substantial improvement in the SNDR. A simple and accurate calibration procedure for the ADC is presented thanks to body biasing. The ADC is designed in 22 nm FDSOI while consuming 1.65 mW from a 0.8 V supply with a core chip area of 0.00074 mm(2). The Walden figure-of-merit of 19.5 fJ/conversion-step at Nyquist rate making it one of the lowest among recently published medium resolution SAR ADCs.

引用

页码：52 / 57

页数：6

共 29 条

[1] Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI
Cordova, David
Cops, Wim
Deval, Yann
Rivet, Francois
Lapuyade, Herve
Nodenot, Nicolas
Piccin, Yohan
VLSI-SOC: DESIGN TRENDS, VLSI-SOC 2020, 2021, 621 : 1 - 19
[2] A Hierarchical Track and Hold Circuit for High Speed ADC-Based Receivers in 22nm FDSOI
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Cops, Wim
Deval, Yann
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Nodenot, Nicolas
Piccin, Yohan
2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2019, : 358 - 361
[3] A 7b 400 MS/s pipelined SAR ADC in 65 nm CMOS
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[4] A 39GHz Bandwidth, 2.5GS/s 7-bit SAR ADC in 22nm FDSOI CMOS
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[5] A Low-Power 9-bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS
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[6] A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI
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[7] 1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applications
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IET CIRCUITS DEVICES & SYSTEMS, 2019, 13 (06) : 857 - 862
[8] An 80MHz-BW 640MS/s Time-Interleaved Passive Noise-Shaping SAR ADC in 22nm FDSOI Process
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[9] A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
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Analog Integrated Circuits and Signal Processing, 2021, 106 : 321 - 337
[10] A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
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