Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction

被引：28

作者：

Akbari, Meysam ^{[1
]}

Hashemipour, Omid ^{[2
]}

机构：

[1] Shahid Beheshti Univ, Microelect Lab, GC, Tehran, Iran

[2] Shahid Beheshti Univ, Dept Elect & Copmuter Engn, GC, Tehran, Iran

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2015年 / 83卷 / 03期

关键词：

Flicker noise; Strong inversion; Folded cascode; CMOS amplifier; Design methodology; TRANSCONDUCTANCE; AMPLIFIER; PERFORMANCE;

D O I：

10.1007/s10470-015-0535-x

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new methodology for design of folded cascode (FC) and recycling folded cascode (RFC) OTAs based on 1/f noise reduction is presented. With a new formulation for input referred flicker noise based on Gm/Id characteristic in all operation regions significantly enhance of the noise performance is achieved. Also, this technique leads to the larger DC gain and gain-bandwidth, and phase margin degeneration. The amplifiers were simulated in the 0.18 mu m CMOS technology and the simulation results confirm the theoretical analyses. Proposed design methodology exhibits 50 % reduction of input voltage noise @ 1 Hz for RFC compared to the FC amplifier, without increasing the power consumption and silicon area.

引用

页码：343 / 352

页数：10

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