Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction

In this paper, a new methodology for design of folded cascode (FC) and recycling folded cascode (RFC) OTAs based on 1/f noise reduction is presented. With a new formulation for input referred flicker noise based on Gm/Id characteristic in all operation regions significantly enhance of the noise performance is achieved. Also, this technique leads to the larger DC gain and gain-bandwidth, and phase margin degeneration. The amplifiers were simulated in the 0.18 mu m CMOS technology and the simulation results confirm the theoretical analyses. Proposed design methodology exhibits 50 % reduction of input voltage noise @ 1 Hz for RFC compared to the FC amplifier, without increasing the power consumption and silicon area.