C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing

被引:40
|
作者
Jiang, Zhewei [1 ]
Yin, Shihui [2 ]
Seo, Jae-Sun [2 ]
Seok, Mingoo [1 ]
机构
[1] Columbia Univ, Elect Engn Dept, New York, NY 10027 USA
[2] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85287 USA
来源
IEEE SOLID-STATE CIRCUITS LETTERS | 2019年 / 2卷 / 09期
关键词
Capacitive coupling; in-memory-computing (IMC); machine learning accelerator; mixed-signal processing; neural network;
D O I
10.1109/LSSC.2019.2934831
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 x 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975x smaller energy-delay product than conventional digital processors.
引用
收藏
页码:131 / 134
页数:4
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