共 50 条
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- [33] Test Generation of Path Delay Faults Induced by Defects in Power TSV 2013 22ND ASIAN TEST SYMPOSIUM (ATS), 2013, : 43 - 48
- [34] Reduction of target fault list for crosstalk-induced delay faults by using layout constraints PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 242 - 247
- [35] Design of an optimal test pattern generator for built-in self testing of path delay faults ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 205 - 210
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- [38] Built-in self-test for state faults induced by crosstalk in sequential circuits 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 469 - 469
- [39] Modeling crosstalk induced delay 4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 189 - 194
- [40] Test generation for global delay faults INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 433 - 442