AN FPGA HARDWARE/SOFTWARE CO-DESIGN TOWARDS EVOLVABLE SPIKING NEURAL NETWORKS FOR ROBOTICS APPLICATION

被引:17
|
作者
Johnston, S. P. [1 ]
Prasad, G. [1 ]
Maguire, L. [1 ]
Mcginnity, T. M. [1 ]
机构
[1] Univ Ulster, Sch Comp & Intelligent Syst, Intelligent Syst Res Ctr, Derry BT47 7JL, North Ireland
关键词
FPGA; ESNN; hardware/software co-design; TIMING-DEPENDENT PLASTICITY; LEARNING ALGORITHMS; IMPLEMENTATION;
D O I
10.1142/S0129065710002541
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.
引用
收藏
页码:447 / 461
页数:15
相关论文
共 50 条
  • [1] Hardware/Software Co-design for Evolvable Hardware by Genetic Algorithm
    Shang, Qianyi
    Chen, Lijun
    Tong, Ruoxiong
    PROCEEDINGS OF 2020 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE AND INFORMATION SYSTEMS (ICAIIS), 2020, : 306 - 309
  • [2] Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks
    Apolinario, Marco Paul E.
    Kosta, Adarsh Kumar
    Saxena, Utkarsh
    Roy, Kaushik
    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 2024, 12 (01) : 35 - 47
  • [3] Towards automating hardware/software co-design
    El-Kharashi, MW
    El-Malaki, MH
    Hammad, S
    Salem, A
    Wahdan, A
    4TH IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2004, : 189 - 192
  • [4] Hardware-Software Co-Design of AES on FPGA
    Baskaran, Saambhavi
    Rajalakshmi, Pachamuthu
    PROCEEDINGS OF THE 2012 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI'12), 2012, : 1118 - 1122
  • [5] On Teaching Hardware/Software Co-design using FPGA
    Bencheva, N.
    Kostadinov, N.
    Ruseva, Y.
    ELEKTRONIKA IR ELEKTROTECHNIKA, 2010, (06) : 91 - 94
  • [6] LACC:a hardware and software co-design accelerator for deep neural networks
    于涌
    Zhi Tian
    Zhou Shengyuan
    HighTechnologyLetters, 2021, 27 (01) : 62 - 67
  • [7] Hardware-software Co-design of Slimmed Optical Neural Networks
    Zhao, Zheng
    Liu, Derong
    Li, Meng
    Ying, Zhoufeng
    Zhang, Lu
    Xu, Biying
    Yu, Bei
    Chen, Ray T.
    Pan, David Z.
    24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019), 2019, : 705 - 710
  • [8] Software/Hardware Co-Design Optimization for Sparse Convolutional Neural Networks
    Hu, Wei
    Dong, Yong
    Liu, Fang
    Jiao, Qiang
    2021 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS (SMC), 2021, : 2069 - 2074
  • [9] LACC: a hardware and software co-design accelerator for deep neural networks
    Yu Y.
    Zhi T.
    Zhou S.
    High Technology Letters, 2021, 27 (01) : 62 - 67
  • [10] FPGA-Based Software Profiler for Hardware/Software Co-design
    Saad, El-Sayed M.
    Awadalla, Medhat H. A.
    El-Deen, Kareem Ezz
    NRSC: 2009 NATIONAL RADIO SCIENCE CONFERENCE: NRSC 2009, VOLS 1 AND 2, 2009, : 475 - 482