An experimental low-power CMOS pipeline ADC using feedforward sample-and-hold amplifier

被引：0

作者：

Tam, CT ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] Univ Waterloo, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada

来源：

UNIVERSITY AND INDUSTRY - PARTNERS IN SUCCESS, CONFERENCE PROCEEDINGS VOLS 1-2 | 1998年

关键词：

ADC; CMOS; digital error correction (DEC); digital-to-analog converter (DAC); operational amplifier (op-amp); SHA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an experimental CMOS 3.3V 10-bit 1.5-bit-per-stage pipeline analog-to-digital converter (ADC) using a feedforward sample-and-hold amplifier (SHA) in a 5V 0.8 mu m BICMOS process. Test results show that it achieves up to 8 bits of resolution. The chip consumes a power of 35mW at a maximum conversion rate of 10MS/s. The modified SHA offers several advantages such as relaxed gain requirement, lower power consumption and smaller area.

引用

页码：257 / 260

页数：4

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