DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE EVEN PARITY CHECKER AND GENERATOR

被引：0
|
作者：
Gayathri, S. S. [1 ]
Ananthalakshmi, A. V. [2 ]
机构：
[1] Dhanalakshmi Srinivasan Inst Res Technol, Dept ECE, Siruvachur, Tamil Nadu, India
[2] Pondicherry Engn Coll, Dept ECE, Pondicherry, India
来源：
2014 International Conference on Science Engineering and Management Research (ICSEMR) | 2014年
关键词：
Reversible logic; Parity checker and generator; Feynman gate; Toffoli gate; New gate; Peres gate;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.
引用
收藏
页数：4
相关论文
共 50 条
  • [31] Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator
    Amal K Ghosh
    OptoelectronicsLetters, 2010, 6 (05) : 325 - 327
  • [32] Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator
    Ghosh A.K.
    Optoelectronics Letters, 2010, 6 (05) : 325 - 327
  • [33] Research on the Method of Parity Checker Design Based on Evolvable Hardware
    Wang, Kuifu
    Yan, Jingfeng
    APPLIED INFORMATICS AND COMMUNICATION, PT III, 2011, 226 : 119 - 124
  • [34] An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
    Fiser, Petr
    Kubalik, Pavel
    Kubatova, Hana
    11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 96 - 99
  • [35] An optimal design of conservative efficient reversible parity logic circuits using QCA
    Bahar A.N.
    Ahmad F.
    Nahid N.M.
    Kamrul Hassan M.
    Abdullah-Al-Shafi M.
    Ahmed K.
    International Journal of Information Technology, 2019, 11 (4) : 785 - 794
  • [36] Design and implementation of a GUI for the TLC model checker
    Wang, B.
    Pronk, C.
    ACM SIGPLAN NOTICES, 2006, 41 (12) : 38 - 43
  • [37] 72-KBIT DYNAMIC RAM INCLUDES ITS OWN PARITY GENERATOR AND CHECKER
    LEONARD, M
    ELECTRONIC PRODUCTS MAGAZINE, 1986, 28 (18): : 27 - 28
  • [38] Design and performance analysis of 2D photonic crystal-based all-optical parity generator and checker
    Michael, Margarat
    Britto, Elizabeth Caroline
    Nizar, Mohamed
    Anbarasan, Swedha Darshini
    JOURNAL OF OPTICS-INDIA, 2024, 53 (04): : 3708 - 3725
  • [39] Design and Analysis of Novel Non-Reversible & Reversible Parity Generator and Detector in Quantum Cellular Automata using Feynman Gate
    Tripathi N.
    Fazili M.M.
    Jahangir R.
    Micro and Nanosystems, 2022, 14 (03) : 256 - 262
  • [40] All-optical 4-bit parity checker design
    Srivastava, Vikrant K.
    Priye, Vishnu
    OPTICA APPLICATA, 2011, 41 (01) : 157 - 164
12345