DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE EVEN PARITY CHECKER AND GENERATOR

被引：0
|
作者：
Gayathri, S. S. [1 ]
Ananthalakshmi, A. V. [2 ]
机构：
[1] Dhanalakshmi Srinivasan Inst Res Technol, Dept ECE, Siruvachur, Tamil Nadu, India
[2] Pondicherry Engn Coll, Dept ECE, Pondicherry, India
来源：
2014 International Conference on Science Engineering and Management Research (ICSEMR) | 2014年
关键词：
Reversible logic; Parity checker and generator; Feynman gate; Toffoli gate; New gate; Peres gate;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.
引用
收藏
页数：4
相关论文
共 50 条
  • [1] Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata
    Ali Norouzi
    Saeed Rasouli Heikalabad
    Photonic Network Communications, 2019, 38 : 231 - 243
  • [2] Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata
    Norouzi, Ali
    Heikalabad, Saeed Rasouli
    PHOTONIC NETWORK COMMUNICATIONS, 2019, 38 (02) : 231 - 243
  • [3] Design of Practical Parity Generator and Parity Checker Circuits in QCA
    Kumar, Dharmendra
    Kumar, Chintoo
    Gautam, Shipra
    Mitra, Debasis
    2017 3RD IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS), 2017, : 28 - 33
  • [4] A Novel Area Efficient Parity Generator and Checker Circuits Design Using QCA
    Lakshmi, K. Bhagya
    Tejaswi, S.
    Vamsi, S. Chandra
    Jeevanarani, B.
    PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT-2020), 2020, : 1108 - 1113
  • [5] Power Efficient Odd Parity Generator & Checker Circuits
    Vanlalchaka, Reginald H.
    Roy, Soumik
    2013 1ST INTERNATIONAL CONFERENCE ON EMERGING TRENDS AND APPLICATIONS IN COMPUTER SCIENCE (ICETACS), 2013, : 65 - 69
  • [6] Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication
    Das, Jadav Chandra
    De, Debashis
    FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2016, 17 (03) : 224 - 236
  • [7] Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication
    Jadav Chandra DAS
    Debashis DE
    Frontiers of Information Technology & Electronic Engineering, 2016, 17 (03) : 224 - 236
  • [8] Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication
    Jadav Chandra Das
    Debashis De
    Frontiers of Information Technology & Electronic Engineering, 2016, 17 : 224 - 236
  • [9] PARITY CHECKER/GENERATOR.
    Torres, A.
    IBM technical disclosure bulletin, 1984, 27 (4 A): : 1889 - 1892
  • [10] Implementation and Performance analysis of single layered reversible Parity generator and Parity checker Circuits using Quantum Dot Cellular Automata paradigm
    Waje, Manisha G.
    Dakhole, P. K.
    2015 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2015, : 175 - 180
12345