Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test

被引：0
|
作者：
Yen, Cheng-Cheng [1 ]
Ker, Ming-Dou [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Nanoelect & Gigascale Syst Lab, Hsinchu 30039, Taiwan
来源：
IPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | 2007年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mu m CMOS technology.
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页码：253 / +
页数：2
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