Low Power 14T Hybrid Full Adder Cell

被引：0

作者：

Sugandha, Chauhan ^{[1
]}

Tripti, Sharma ^{[1
]}

机构：

[1] Chandigarh Univ Gharuan, Dept Elect & Commun Engn, Mohali, Punjab, India

来源：

PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON FRONTIERS IN INTELLIGENT COMPUTING: THEORY AND APPLICATIONS, (FICTA 2016), VOL 2 | 2017年 / 516卷

关键词：

Power consumption; Delay; Parasitic capacitance; Area; Power-delay product; CMOS; DESIGN; LOGIC;

D O I：

10.1007/978-981-10-3156-4_15

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The performance of the adder entirely influenced by the performance of its basic modules. In this paper, a new hybrid 1-bit 14 transistor full adder design is proposed. The proposed circuit has been implemented using pass gate as well as CMOS logic hence named hybrid. The main design objective for this circuit is low power consumption and full voltage swing at a low supply voltage. As a result the proposed adder cell remarkably improves the power consumption, power-delay product and has less parasitic capacitance when compared to the 16T design. It also improves layout area by 7-8 % than its peer design. All simulations are performed at 90 & 45 nm process technology on Synopsys tool.

引用

页码：151 / 160

页数：10

共 50 条

[21] Design and Performance Analysis of Low-Power Hybrid Full Adder Circuit
Upadhyay, Rahul Mani
Kumar, Manish
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2021, 16 (01): : 13 - 23
[22] A New Design of Low Power High Speed Hybrid CMOS Full Adder
Agarwal, Mayur
Agrawal, Neha
Alam, Md. Anis
2014 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2014, : 448 - 452
[23] A Novel Low Power Multilpier and Full Adder using Hybrid CMOS Logic
Vani, A. Swetha
Lokesh, M. Ratna
Devi, B. Sowmya
Kushal, A. K. K. V. N. S.
Kumar, Aylapogu Pramod
2017 INTERNATIONAL CONFERENCE OF ELECTRONICS, COMMUNICATION AND AEROSPACE TECHNOLOGY (ICECA), VOL 1, 2017, : 303 - 307
[24] Investigating the 20T Hybrid Full Adder Design for Low Power and High-Performance Computing
Goel, Satvik
Kumar, Saurabh
Tripathi, Ritam
Bajpai, Shivansh
Soni, Rahul
Chauhan, R. K.
IETE JOURNAL OF RESEARCH, 2024, 70 (12) : 8684 - 8691
[25] A novel Low Power Multiplexer-Based full adder cell
Alhalabi, B
Al-Sheraidah, A
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 1433 - 1436
[26] On the design of low power 1-bit full adder cell
Maeen, Mehrdad
Foroutan, Vahid
Navi, Keivan
IEICE ELECTRONICS EXPRESS, 2009, 6 (16): : 1148 - 1154
[27] A low power and energy efficient 4:2 precise compressor based on novel 14T hybrid full adders in 10 nm wrap gate CNTFET technology
Jooq, Mohammad Khaleqi Qaleh
Bozorgmehr, Ali
Mirzakuchaki, Sattar
MICROELECTRONICS JOURNAL, 2020, 104
[28] Modeling and Simulation of Low Power 14 T Full Adder with Reduced Ground Bounce Noise at 45 nm Technology
Singh, Raghvendra
Akashe, Shyam
2013 STUDENTS CONFERENCE ON ENGINEERING AND SYSTEMS (SCES): INSPIRING ENGINEERING AND SYSTEMS FOR SUSTAINABLE DEVELOPMENT, 2013,
[29] Ultra Low Power Full Adder Topologies
Moradi, Farshad
Wisland, Dag T.
Mahmoodi, Hamid
Aunet, Snorre
Cao, Tuan Vu
Peiravi, Ali
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 3158 - +
[30] OPTIMIZED LOW POWER FULL ADDER DESIGN
Thenmozhi, V.
Muthaiah, R.
2017 INTERNATIONAL CONFERENCE ON NETWORKS & ADVANCES IN COMPUTATIONAL TECHNOLOGIES (NETACT), 2017, : 86 - 89

← 1 2 3 4 5 →