Failure analysis of full delamination on the stacked die leaded packages

被引:5
|
作者
Lin, TY [1 ]
Xiong, ZP [1 ]
Yao, YF [1 ]
Tok, L [1 ]
Yue, ZY [1 ]
Njoman, B [1 ]
Chua, KH [1 ]
机构
[1] Agere Syst Singapore Pte Ltd, Singapore 349278, Singapore
来源
53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS | 2003年
关键词
D O I
10.1109/ECTC.2003.1216440
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
There has been significant demand for stacked die technology during the paste few years. The stacked die devices are mainly used in portable consumer products. This kind of silicon integration technology provides flexibility in space reduction, weight savings and excellent electrical functionality. In this article, the samples with stacked die construction were built into the leaded package. It was found that one of the test vehicles had full delamination at the leadframe paddle/mold compound interface after 100 temperature cycles (-55C to 150C) with moisture preconditioning at level 3 (60C/60%RH for 40 hours) although the electrical test passed 1000 temperature cycles. The fish bone diagram was used to identify the possible failure root causes. The material, process and design factors were extensively evaluated by the experiments and finite element analysis. The ealuation results showed that die attach paste voids were major factors affecting the package integrity, and could produce the delamination initiation at the edge of the die attach paste and propagate down to the leadframe paddle/mold compound interface due to high stress concentration and weak adhesion strength. The finite. element analyses were implemented to address the stress distribution in the stacked die package and verified by the actual C-SAM results. It demonstrated that the excellent package integrity could be achievable by applying the void-free die attach paste and improving the adhesion strength at the leadframe paddle level.
引用
收藏
页码:1170 / 1175
页数:6
相关论文
共 50 条
  • [31] Compact modeling approaches to multiple die stacked chip scale packages
    Garcia, EA
    Chiu, CP
    NINETEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, 2003, : 160 - 167
  • [32] Interfacial Delamination Characterization and Thermo-mechanical Reliability of Stacked Die Package by Finite Element Analysis
    Chen, Bin
    Wang, Hong-Guang
    Lyu, Guang-Chao
    Yang, Bing-Xian
    Hu, Wei-Lin
    Zhang, Xin-Ping
    2022 23RD INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2022,
  • [33] Effects of Material Properties and Thickness of Die Attach on Package Delamination of IC Packages
    Chang, Chia-Lung
    Chang, Cheng-Lun
    Wang, Ying-Long
    ADVANCED MECHANICAL DESIGN, PTS 1-3, 2012, 479-481 : 2564 - 2567
  • [34] Application of submodeling technique to transient drop impact analysis of board-level stacked die packages
    Hsu, Hsiang-Chen
    Hsu, Yu-Chia
    Lee, Hui-Yu
    Yeh, Chang-Lin
    Lai, Yi-Shao
    EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 412 - 418
  • [35] An analysis of interface delamination in flip-chip packages
    Mercado, LL
    Sarihan, V
    Hauck, T
    50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 1332 - 1337
  • [36] Parametric analysis of steam driven delamination in electronics packages
    Lam, DCC
    Chong, IT
    Tong, P
    IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2000, 23 (03): : 208 - 213
  • [37] Study on the delamination between adhesive film and silicon in stacked-die packaging
    Liao, Yinxing
    Li, Xiao
    Wang, Jun
    2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012), 2012, : 1314 - 1316
  • [38] Coupled power and thermal cycling characteristics and reliability of stacked-die packages
    Wang, Tong Hong
    Lee, Chang-Chi
    Lai, Yi-Shao
    Wang, Ching-Chun
    2007 INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 202 - 206
  • [39] A simple method for thermal characterization of stacked die electronic packages in staggered arrangement
    Bharadwaj B.R.
    Kandagadla S.
    Nadkarni P.J.
    Krishna V.
    Seetharam T.R.
    Seetharamu K.N.
    Journal of Microelectronics and Electronic Packaging, 2018, 15 (03): : 117 - 125
  • [40] Optimization of packaging materials and design for thermal management in stacked-die packages
    Moon, Sung-won
    Dizon, Michael
    Chiu, Chia-pin
    Garcia, Enrico
    2006 PROCEEDINGS 10TH INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONICS SYSTEMS, VOLS 1 AND 2, 2006, : 1226 - +