Vt-Conscious Repeater Insertion in Power-Managed VLSI

被引：0
|
作者：
Zarrabi, Houman [1 ]
Al-Khalili, Asim [1 ]
Savaria, Yvon [2 ]
机构：
[1] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ, Canada
[2] Ecole Polytech Montreal, Dept Elect Engn, Montreal, PQ, Canada
来源：
2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC) | 2014年
关键词：
Interconnections; Repeater Insertion; Dynamic Power Management; VLSI;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, methods for the design space exploration of interconnection repeaters in deep-sub-micron power-managed VLSI are presented. These methods consider the system supply-voltage as well as the device threshold-voltage, as the design parameters; and guarantee that the designed interconnections are energy-optimal while they meet their performance objectives in all the system operating states. These methods take the output resistance of the repeaters into account, when the system supply-voltage, system operating frequency as well as the device threshold-voltage requirements change. Utilizing the proposed techniques, a multi-cycle 10-mm long bus is designed for some design objectives. HSPICE simulations confirm that the designed bus is energy-optimal, and that it meets its performance targets in all the system operating states.
引用
收藏
页码：99 / 102
页数：4
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