Vt-Conscious Repeater Insertion in Power-Managed VLSI

In this paper, methods for the design space exploration of interconnection repeaters in deep-sub-micron power-managed VLSI are presented. These methods consider the system supply-voltage as well as the device threshold-voltage, as the design parameters; and guarantee that the designed interconnections are energy-optimal while they meet their performance objectives in all the system operating states. These methods take the output resistance of the repeaters into account, when the system supply-voltage, system operating frequency as well as the device threshold-voltage requirements change. Utilizing the proposed techniques, a multi-cycle 10-mm long bus is designed for some design objectives. HSPICE simulations confirm that the designed bus is energy-optimal, and that it meets its performance targets in all the system operating states.