Snapback circuit model for cascoded NMOS ESD over-voltage protection structures

被引：6

作者：

Vassilev, V ^{[1
]}

Lorenzini, M ^{[1
]}

Jansen, P ^{[1
]}

Vashchenko, V ^{[1
]}

Yang, JJ ^{[1
]}

Concannon, A ^{[1
]}

Archer, D ^{[1
]}

Groeseneken, G ^{[1
]}

Natarajan, MI ^{[1
]}

Terbeek, M ^{[1
]}

Thijs, S ^{[1
]}

Choi, BJ ^{[1
]}

Steyaert, M ^{[1
]}

Maes, HE ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256938

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents an equivalent circuit snapback model for the ESD domain operation of merged cascoded NMOS devices. The model reflects the specific breakdown operation of the structure at different gate bias conditions. An example for optimisation of the ESD behaviour of an output driver, utilising this protection device, is presented.

引用

页码：561 / 564

页数：4

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