Impact of the Octagonal Layout Style for MOSFETs using 180nm Bulk CMOS ICs Technology Node

被引：0
|
作者：
Loesch, Denis Santos [1 ]
Gimenez, Salvador Pinillos [1 ]
Swart, Jacobus Willibrordus [2 ]
da Silva, Gabriel Augusto [1 ]
机构：
[1] Ctr Univ FEI FEI, Dept Elect Engn, Sao Bernardo Do Campo, Brazil
[2] Univ Estadual Campinas, Semicond Instruments & Photon Dept, Sao Paulo, Brazil
来源：
2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO) | 2018年
基金：
巴西圣保罗研究基金会;
关键词：
Octagonal layout style; OCTO MOSFET; LCE; PAMDLE; electrical characterization;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper aims to evaluate the impact of the octagonal layout style for MOSFETs regarding the 180nm Bulk CMOS ICs technology node. The main results of this study show that the MOSFETs with octagonal gate geometries are capable of improving the drain current, Early voltage, intrinsic voltage gain, and on-state drain to source resistance about 150%, 800%, 66% and 50%, respectively, in relation to the standard rectangular MOSFET counterparts, regarding the same bias conditions. Therefore, the LCE and PAMDLE effects continue being actives regarding this 180 nm Bulk CMOS ICs technology node.
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页数：4
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