All-Digital 0.016mm2 Reconfigurable Sensor-ADC Using 4CKES-TAD in 65nm Digital CMOS

被引:0
|
作者
Watanabe, Takamoto [1 ]
Hou, Yu [2 ]
Miyahara, Masaya [2 ]
Matsuzawa, Akira [2 ]
机构
[1] DENSO CORP, Kariya, Aichi, Japan
[2] Tokyo Inst Technol, Tokyo, Japan
关键词
RESOLUTION; CONVERTER; POWER;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An all-digital reconfigurable (10-to-16-bit) sensor ADC based on TAD (Time A/D converter) is completely digital, using a ring-delay-line RDL driven by an input voltage V-in as its power supply. This method realized 16.2bit/100ksps/37.5 mu W from 0.6V supply without any static current using a 0.016mm(2) prototype 4CKES (4-clock-edge-shift) TAD in a 65nm digital CMOS. Resolutions can be controlled by setting its conversion time T-cv. A 13.8bit/1Msps/75.4 mu W or 10.5bit/10Msps/93.2 mu W operation is also experimentally confirmed using 0.6V supply. Finally, correction of nonlinearity characteristics has been discussed using differential-setup processing method.
引用
收藏
页码:21 / 24
页数:4
相关论文
共 42 条
  • [21] An All-Digital Quadrature RF Transmitter Front-End Using 3-bit ΣΔ Modulators in 65-mm CMOS
    Liu, Weixing
    Li, Feiyi
    Xue, Pan
    Hong, Zhiliang
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1081 - 1083
  • [22] 12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process
    Lee, Sanggeun
    Oh, Taehyoun
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2021, 21 (02) : 152 - 156
  • [23] A 20-to-1000MHz ± 14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS
    Elkholy, Ahmed
    Elshazly, Amr
    Saxena, Saurabh
    Shu, Guanghua
    Hanumolu, Pavan Kumar
    2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2014, 57 : 272 - +
  • [24] All-digital reconfigurable IR-UWB pulse generator using BPSK modulation in 130nm RF-CMOS process
    Moreira, Luiz Carlos
    Fontebasso Neto, Jose
    Ferauche, Thiago
    Silva Novaes, Guilherme Apolinario
    Torres Rios, Emmanuel
    2017 IEEE 8TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2017,
  • [25] A Resolution-Adaptive 8 mm2 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS
    Castaneda, Oscar
    Boynton, Zachariah
    Mirfarshbafan, Seyed Hadi
    Huang, Shimin
    Ye, Jamie C.
    Molnar, Alyosha
    Studer, Christoph
    ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), 2021, : 247 - 250
  • [26] A 0.03mm2, 40nm CMOS 1.5GS/s All-Digital Complementary PWM-GRO
    Prefasi, E.
    Gutierrez, E.
    Hernandez, L.
    Paton, S.
    Walter, S.
    Gaier, U.
    2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2014, : 116 - 119
  • [27] A 0.016 mm2 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS
    Zhu, Junheng
    Choi, Woo-Seok
    Hanumolu, Pavan Kumar
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (08) : 2186 - 2194
  • [28] A 3 MHz-to-1.8 GHz 94 OAT-to-9.5 mW 0.0153-mm2 All-Digital Delay-Locked Loop in 65-nm CMOS
    Cheng, Chun-Yuan
    Wang, Jinn-Shyan
    Chou, Pei-Yuan
    Chen, Shiou-Ching
    Sun, Chi-Tien
    Chu, Yuan-Hua
    Yang, Tzu-Yi
    2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2014, : 361 - 364
  • [29] A 6.7 MHz to 1.24 GHz 0.0318 mm2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS
    Hsieh, Min-Han
    Chen, Liang-Hsin
    Liu, Shen-Iuan
    Chen, Charlie Chung-Ping
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (02) : 412 - 427
  • [30] A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm Using Novel Residue Boosting
    Park, Joonsung
    Nagaraj, Krishnaswamy
    Ash, Mikel
    Kumar, Ajay
    2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2017,